This invention relates to multiprocessor central controllers, and it relates, more particularly, to an optimized memory configuration technique. This invention is related to the invention of German patent application P 33 34 773.5, which corresponds to U.S. patent application Ser. No. 651,954 filed Sept. 19, 1984, now abandoned.
Such a central control unit must be extremely tolerant of errors, that is, errors that occur should be rapidly detected, and defective sections of the central memory, or those sufficiently suspected of error, rapidly eliminated before additional errors result from the error which can affect the operation of the switching system. For that reason, the control units of the memory blocks of this central control unit and typically also the bus system and the central processors are redundant and protected against error, apart from a possible tolerable timing slip, and driven in precise synchronism in parallel.
Furthermore, such a central control unit should be capable of extremely high operational availability despite uninterrupted operation, that is any serious malfunctions must be limited to a few seconds or minutes per year, at most. In other words, the central control unit should have a minimum of downtime. In addition, the main memory of the central control unit should virtually never bring about a completely failure of the switching operation. The switching operation should also continue to operate with the highest possible tolerance for errors, during the failure and isolation of one of the, often diverse, elements of the central memory.